1. Technical Field
The present invention relates to memory devices and, more particularly, to accessing memory cells of a volatile memory device.
2. Background Art
Computing systems generally rely on memory devices to store information. Such memory devices may be divided into two general types. First, volatile memory devices which require power to maintain correctness of the stored information. Second, non-volatile memory devices which maintain the stored information even after power is cut off.
One common type of volatile memory device is Dynamic Random Access Memory (DRAM). DRAM devices generally provide significantly improved performance over mechanical storage devices (such as hard disks), while providing lower cost, higher storage densities and less power consumption in comparison to other memory technologies, including and most notably, static random access memory (SRAM) devices. However, these benefits come at the cost of incurring various delays in accessing the memory cells making up a DRAM device, both at regular intervals, and in the time periods immediately before and after each access to either read data from the memory cells or to write data to the memory cells.
DRAMs generally store each bit of data in a separate capacitor within an integrated circuit. Since capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh requirement and other design considerations, DRAMs designers impose various timing constraints on operations within a DRAM to maintain correctness. One such constraint is a precharge requirement. In particular, when access is requested to a different row (also referred to as a Bit Line (BL)) in a DRAM, the current row has to be first deactivated by issuing a “precharge” command. The precharge command will cause the sense amplifiers to switch off and the bit lines to be precharged to matching voltages that are intermediate between high and low logic levels. After a certain row precharge time period delay (also referred to as tRP), an “activate” command may be issued to activate the next row to be accessed.
It is refresh operations, precharge operations, activate operations as well as other maintenance operations that impose the various delays that are suffered as a result of employing DRAM technology. These delays have the effect of limiting the rate at which data may be written to or read from DRAM devices, and although components such as processors have made great strides in becoming ever faster, comparatively little progress has been made in increasing the rate of accesses for DRAM technology.